1. Field
Embodiments are directed to ferroelectric random access memory (FeRAM or FRAM) devices and methods of manufacturing the same. More particularly, example embodiments described herein relate to a ferroelectric random access memory device including a ferroelectric capacitor, and a method of manufacturing the ferroelectric random access memory device.
2. Description of the Related Art
Generally, a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, etc., can lose stored data when power is removed from the volatile memory device. In contrast, a non-volatile memory device such as an electrically programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) device, a flash EEPROM memory device, etc., does not lose data when a power is not applied to the non-volatile memory device. Thus, the non-volatile memory device can be widely used. However, the volatile memory device can be limited in application, because it is necessary to continuously apply a power to the volatile memory device in order for the volatile memory device to store data. Further, non-volatile memory devices often have a low degree of integration, a slow operational speed, and requires a high voltage, etc.
Therefore, in order to solve the abovementioned problems, a semiconductor memory device including a ferroelectric material has been widely considered because this device provides beneficial features of both volatile memory devices and non-volatile memory devices. In particular, a ferroelectric capacitor can be combined with an access transistor, a bit line, and a plate line to form a memory cell
Generally, the ferroelectric material can correspond to a non-linear dielectric material that can exhibit a hysteresis loop in accordance with an electric field caused by a dielectric polarization. A ferroelectric random access memory (FRAM) device comprising the ferroelectric material can possess features of a non-volatile memory device due to the dielectric polarization characteristics of the ferroelectric material.
Thus, the FRAM device can have a structure including the ferroelectric material in place of a conventional dielectric layer of a DRAM device. However, the FRAM device can be used as a memory device by applying a voltage to the ferroelectric material to change the polarization of the ferroelectric material. Thus, upper electrodes of the FRAM device are generally configured to receive the voltage via a plate line. For this reason, the upper electrodes of capacitors in the FRAM device are electrically connected to plate lines.
In the FRAM device, a memory cell must be sensed to determine the corresponding bit setting in the memory cell. However, methods of sensing cells can be different from each other in accordance with arrangement structures of bit lines. The arrangement structures of the bit lines in the FRAM device can be classified into a folded bit line structure and an open bit line structure.
The folded bit line structure can include a bit line and a bit line bar in parallel with each other. In the FRAM device having the folded bit line structure, when a selected single word line is operated, cells can be operated one by one in a direction of extension of the bit line. Particularly, when the selected word line is activated, data in the cell can be output from a bit line connected to the selected word line. The data can be compared with data in a bit line bar adjacent and parallel to the bit line in order to sense the data in the cell. Therefore, because a single core sense amplifier is connected to both the bit line and the adjacent bit line bar to perform the comparison, an area where the core sense amplifier is formed can be sufficiently ensured in a core region, i.e., a region that includes the memory cells.
However, the folded bit line structure can include two word lines in a region where a single cell can be formed. That is, the two word lines can be arranged in a central portion and an edge portion of an active region where a unit cell can be formed. Thus, a parasitic capacitance between the bit line and the word line can be significantly increased. The increased parasitic capacitance can cause a difference between a noise signal of an output signal and a noise signal of the parasitic capacitance, so that a sensing margin does not effectively discriminate between states of the data of the selected cell, i.e., between a programmed cell and an erased cell. Particularly, when forming a highly integrated FRAM device, the parasitic capacitance can have a greater influence on the highly integrated FRAM device. As a result, the highly integrated FRAM device can have frequent malfunctions and complicated designs.
In contrast, the open bit line structure can include a bit line and a bit line bar arranged at both sides of a sense amplifier in a core region. Particularly, in a FRAM device having the open bit line structure, when a selected single word line can be operated, all of the cells can be operated in a direction of extension of the bit line. That is, when the selected word line is activated, data in a given cell can be output from both the bit line and the bit line bar connected to the selected word line. Thus, the data output from the bit line can be compared with the data output from the bit line bar arranged in an opposite sector to sense the data in the cell output from the bit line. Further, the data output from the bit line bar can be compared with the data output from the bit line arranged in an opposite sector to sense the data in the cell output from the bit line bar. Therefore, because two core sense amplifiers are provided to the bit line and the bit line bar, respectively, due to their locations in two different sectors, an area where the core sense amplifiers are formed cannot be sufficiently ensured in the core region. Further, because electrical environments between the bit line and the bit line bar connected to the two different core sense amplifiers can be different from each other, signals amplified by the core sense amplifiers can not reliably provide high sensitivity.
However, the FRAM device having the open bit line structure can include relatively more cells in an area compared to those in the FRAM device having the folded bit lint structure. Further, when the FRAM device having the open bit line structure and the FRAM device having the folded bit line structure can include equal numbers of cells in a substantially the same area, the FRAM device having the open bit line structure can have a relatively wide interval between the word lines and a relatively wide interval between the bit lines compared to the those of the FRAM device having the folded bit line structure. Therefore, the FRAM device having the open bit line structure can have a low parasitic capacitance between the bit lines. As a result, the FRAM device having the open bit line structure can have a relatively increased sensing margin compared to that of the FRAM device having the folded bit line structure notwithstanding the abovementioned disadvantages associated with comparisons made between data being output from a bit line and a bit line bar in different sectors.